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The payloads being the principle performance drivers for a satellite, must work properly throughout the lifetime of a satellite to ensure space mission success. An onboard Payload Processing Unit (PPU) is required for payload data storage and its processing. Different design and implementation techniques are employed to achieve a reliable and computationally efficient PPU. Due to the high computational capabilities of modern FPGAs at relatively low power and cost, they can be used in the design and implementation of PPUs. Their support for soft-core processors and real time operating systems helps in increasing the efficiency of PPU in terms of performance and flexibility. This paper presents a fault tolerant PPU using commercial off-the-shelf (COTS) components for Pakistan National Student Satellite -1 (PNSS-1). The proposed PPU implements a LEON3 processor on a Xilinx Virtex 4 FPGA using Triple Modular Redundancy (TMR) and employing RTEMS for real time operations of the PPU software.

Salim Ullah, Laiq Hasan, Asif Ali Khan, Asif Ali Khan, Muhammad Jaleed Khan, Abdullah, Asim Shahzad. (2015) An FPGA Based Fault Tolerant PPU for PNSS-1, Journal of Space Technology , Volume 5, Issue 1.
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