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The decreasing size of the transistor has increased the vulnerability towards faults. Increasing number of cores
on a single chip has made the concept of Network on Chip (NoC) a standard communication backbone among
cores. This facility comes with vulnerability of faults in the system due to decreasing size of transistors. A
permanent fault in the network leads to undesirable consequence such as permanent blocking of flits or failure
of the whole router. Preserving the router in the operational state has a significant impact on the reliability of
the system. Permanent fault in buffers and pipeline stages of the router has a high impact on performance. The
proposed router architecture Protector provides faults protection to both buffers and pipelines stages by
exploiting the concepts of borrowing from other resources, using bypass paths and by creating multiple paths
to reach output. The proposed router incurred an area overhead of 30% as compared to the baseline design.
Reliability analysis using Silicon Protection Factor indicates that the proposed router has better fault tolerance
efficiency as compared to state of the art. Latency analysis using PARSEC and SPLASH-2 benchmarks
indicates proposed router incurs 13% and 16% latency overhead in the presence of faults.
Naveed Khan Baloch, Ayaz Hussain, Muhammad Iram Baig. (2020) Protector: A Permanent Fault Resilient Router Architecture for Network on Chip, Mehran University Research Journal of Engineering & Technology, Volume 39, Issue 4.
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